LnT Infotech is conducting walk-in on Oct 23, 2010 @ Chennai.
Date: 23, October, 2010
Time: 09:30 A.M. to 02:3 P.M.
Venue Details:
L&T Infotech,
Chennai,
TC3, L&T Infotech Park,
Mount Poonamallie Road,
Manapakkam,
Chennai.
POC: Ms. Nethra Nagaraj
Tel : +91-44-2253 5772
Interested candidates please carry your latest resume and last 3 months payslips.
In case if you are unable to walk-in and / or attend the interview, you can send your updated resumes to : Nethra.nagaraj@lntinfotech.com
Experience : 3 - 8 Years
Education: BE / B.Tech / M.Tech / MS / ME
Location: Chennai & Bangalore
Requirements :
- ASIC Implementation (Synthesis, STA, Formal verification) - Experience on high speed synthesis (1 Ghz) using DC, Timing Analysis experience using primetime, Formal Verification using Cadence LEC
- ASIC Gate Level Simulation - Experience in gate level simulation of multi - million ASICs
- ASIC Design Lead - experience in micro architecture, RTL Coding, Hands-on ASIC Synthesis / STA, Supporting physical design team on timing closure, Floorplan and Powerplan
- Modeling - Experience in Modeling using SystemC
- ASIC Verification - Experience in verifying ARM based ASICs, Strong in Testbench architecture, Testplan extraction, SystemVerilog / Spaceman / Vera experience along with OVM or VVM methodology
- DFT Lead - In-depth knowledge of DC / AC tests and on-chip compression techniques, Strong pattern simulation and failure debugging experience with / without SDF, Must have Synopsys DFT Tool experience
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