[EXP] Sasken walk-in on Nov 13 - 14, 2010 - Bangalore

Hi Friends,

Sasken opens up a world of opportunities for professionals in the skills mentioned below.

Date	13th & 14th Nov 2010
Time	9.30 am to 4.00 pm
Venue	Sasken Communication Technologies Ltd, 139/25, 7th Main, West Wing, AmarJyothi Layout, Inner Ring Road, Domlur, Bangalore-71, India Tel: +91 100 39109 1122 Landmark: Opp. Dell office on Inner Ring Road, near Mother Earth Showroom/Hyundai Service Station.

The ideal profile for the below mentioned openings would be Engineering Graduates, Post Graduates or MCA

Embedded Development (Exp: 1 to 3 years)

Development experience in C / C++ on any Embedded system.

Mobile Application/ Middleware/ Device Drivers Development (Exp: 1 to 12 years)

Development experience in Linux Apps, Symbian, Android, Maemo, MeeGo, BREW, WinCE, EMP/SHP/P2K or any RTOS

GSM/ GPRS/ UMTS Protocol Stack Development(L1, L2, L3, L4) (Exp: 1 to 12 years)

Knowledge of Protocol Stack L1 Controller, RLC/ MAC or RR/RRC, NAS Modules, L4 Adaptation / Integration, AT cmds, SIM / USIM, 3GPP specs

Linux Kernel / Middleware / Device drivers (Exp: 2 to 12 years)

Boot Loader Development

Core DD, Clock/ Power Management

DD protocols, HSP UART, Mproc, USB Standards

Linux Kernel level, Middleware & device driver debugging.

Knowledge on Linux Device Security, Multimedia or Connectivity.

L2/L3 Datacom Protocol – Development/Testing (Exp: 3 to 16 years)

Routing Protocols, OSPF, VRRP, Multicast Routing, ISIS, BGP, IPv6, MPLS, MPLS VPN, BGP-VPN, Virtual Router, OSPFng, RIPng, RTM (Routing Table Management), LDP, RSVP-TE/PWE3

Bluetooth Protocol Stack Development and Testing (Exp: 2 to 12 years)

J2ME Development (Exp: 2 to 12 years)

System Verilog / Specman Verification Engineer (Exp: 2 to 12 years)

BFMs development, Test Case Development, Module and SOC Level Verification

SoC Level Physical Designer (Exp: 2 to 12 years)

Place & Route (PnR), CTS, Floor Planning, Timing Closure, Power Planning, IO planning, Synthesis, STA, MAGMA, ICC, Primetime, PTSI, Design Compiler, Apache, Calibre

DFT Engineer (Exp: 2 to 12 years)

JTAG, MBIST, Scan, On-Chip Scan Compression, Fault Models, ATPG & Fault Simulation and AC Scan for at speed testing

You can ask all your friends with the desired qualifications and skill sets to walk in directly to our office on 13th and 14th November 2010 with their latest resume and pay slip