Hi Friends,
IBM is recruiting for the following skill set.
Interested candidates please forward your resumes to : satvelag@in.ibm.com
please mention the Skill, GOM code and in subject line.
User Experience Practitioner
GOM Code : STG-0261982Relevant Experience : 4 years +
Total Experience : 4 years +
Joining Location : Hyderabad
Interview Location : Will be communicated post candidate screening and selection
Description :
User interface design/interaction design/usability for IBM Power Systems/ AIX Operating System.MS/MA or PhD in User Interface Design/Interaction Design/Usability.experience in user interface design/interaction design/usability .User interface design/interaction design/usability methodologies and principles,Experience in planning, executing ,reporting on customer usability studies delivering design documents and prototypes,User interface design prototyping.Simple statistics and research design,Writing and presentation skills,Experience leading projects
Senior Java Developer / Technical Lead -PD TES-STG - ISL
GOM Code : STG-0249271Relevant Experience : 8 years +
Total Experience : 12 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Strong in-depth knowledge and hands on experience on Java, J2EE, JSF, Job DescriptionO, Java Script/CSS, Facelets, Portlets, Struts, XML, DB2, Web services, WPS, SOA, Web 2.0 etc. Development experience with one or more Application and web servers : WebSphere, Apache Axis, Axis2, Tomcat web and application servers. Expertise level in using IDE tools like Eclipse, RAD, RSA, Rational Suite of Tools, Tivoil tools, Rational Clear case etc. Major Field of Study: Software Engineering, Agile Practices, Software Development ,Web Services & related technology.
Sr Application Architect
GOM Code : STG-0251039Relevant Experience : 12 years +
Total Experience : 16 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Strong in-depth knowledge and hands on Java, J2EE, JSF, Struts,XML, DB2, Web services,WPS, SOA etc.Previous experience in designing enterprise strength, Java server side, commercial grade web services software.Ability to clearly articulate architecture in written form and verbally.Development experience with one or more of WebSphere ,Apache Axis, Axis2, Tomcat, System architecture, J2EE, Java, SOA architect, Websphere, Project management, Rational Suite of Tools, Tivoil, Univ/AIX .Major Field of Study:Software Engineering, Software Architecture ,Web Services Architecture & related technology.Web Services standards and specifications knowledge Java server side development experience.
Verification Lead - PD -TES - STG - ISL
GOM Code : STG-0251043Relevant Experience : 7 years +
Total Experience : 10 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Experience in presilicon verification, preferably processors or north bridges .Skills include test writing, debug, creating and maintaining test environment/checkers/monitors, coverage, test plans .Leadership qualities desired: leading group of 3-5 engineers, mentoring, communicating with remote sites, driving functionality.Hands on requirement a must.Education requirements: MS preferred, BS minimum. Good instutions a plus: IITs, RECs, BITs
Post Silicon Validation Engineer - PD - TES - STG - ISL
GOM Code : STG-0251156Relevant Experience : 6 years +
Total Experience : 8 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Experience in post silicon validation in System and ATE environments.Core Skills: Processor & Chipset validation, characterization, analysis, tools development & silicon debug, hands on experience with lab equipment ( bench, system, ATE), developing and executing test plans.MS preferred, BE minimum. Global footprint desired.
OPC /ORC Team Lead -Litho SRDC TES - STG - ISL
GOM Code : STG-0251171Relevant Experience : 5 years+
Total Experience : 8 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Technical lead for a team of Engineers in the OPC/ORC areas. Interact with integration and design teams to provide optical proximity corrections on design patterns and improve manufacturability. Support current methods and develop new techniques (including scripts & tools) to address technology issues and keyword challenges. Candidate should have knowledge in reticle enhancement techniques (RET), exposure to design technology co-optimization with exposure to 45nm, 32 nm technologies. Ability to interface with lithography, integration and design teams. Good interpersonal skills with technical depth required, experience with global teams a pig plus.Software skills requirements - Experience with verification tools such as Mentor Calibre SVRF, Cadence Assura, and/or Cadence Virtuoso. C / C++ coding and shell / iTCL / Perl scripting, object oriented programming a plus, Qualifications : candidates must possess a Degree (MS, PhD.) in Computer Science, Electrical Engineering, Physics, or related fields.
VLSI Design Engineer - TES - STG - ISTL / Signal Integrity Engineers
GOM Code : STG-0251181Relevant Experience : 5+ years
Total Experience : 8 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Signal integrity, hspice, pwrspice, allegro, electromagnetic modeling, ansoft, sigrity, speed2000, noise, cross-talk, simultaneous switching noise, scattering parameters, BER, eye diagrams, jitter, spectraquest.MS preferred, BE minimum. Global footprint desired
Custom Circuit Design - PD - TES - STG - ISL
GOM Code : STG-0251164Relevant Experience : 10 years +
Total Experience : 12 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Active hands on experience in CMOS Custom VLSI Circuit Design using industry leading tools (CADENCE preferred)Thorough understanding of CMOS technology and devices.Familiar with VHDL, schematics entry, circuit simulation (SPICE), custom layout, layout verification methodologies, design for yield and manufacturability, timing analysis, and routing tools.Ability to write CADENCE “SKILL” programming is a plus.Masters Degree, or equivalent .Experience in leading team of circuit designers.
Integration Engineer - PD - TES - STG - ISL
GOM Code : STG-0251175Relevant Experience : 8 years +
Total Experience : 10 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Active hands on experience in CMOS VLSI block level/chip integration using industry leading tools (CADENCE preferred).Knowledge of processor concepts, extensive project experience with placement and automatic routing tools, verification methods, design for yield and manufacturability, and timing analysis.Proven record of product deliverables in the area of VLSI products with special emphasis on frequency, area, and power optimization. Knowledge on hierarchical design methods.Script language knowledge (CADENCE SKILL, TCL, Perl,Methodology development experience is a plus.Ability to learn and adapt to new tools and methodologies .Masters Degree, or equivalent
EDA Developer - EDA- TES - STG - ISTL
GOM Code : STG-0251160Relevant Experience : 4 years +
Total Experience : 8 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Clk EDA Engineer hould have a very sound knowledge of Chip design backend flow especially having worked on Clks for chips. Clock methodology development and routing will be the key focus for the engineer.4+years of experience as a VLSI engineer and full command of VLSI flow. should have a very stong VLSI background. An EE background with strong scriptingskills is desirable. Excellent communication/support skills.Has gone through the clk methodology flow at least 3-4 times. Understands the different clk methodologies and their implementation.
Verification Application Engineer - EDA -TES -STG - ISL
GOM Code : STG-0250977Relevant Experience : 5 years +
Total Experience : 8 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Fusion AE Support Person . Focal point for all Fusion/RTX related problems, issues,questions .Assist Fusion customers with debugging failures both in C++ (see skills below) and Fusion RTX execution .Provide education and documentation as required by local group .C and C++ Fusion/ RTX .Simulation environment (Mesa, AWAN, Bugspray interaction, etc,).Manage release issues related to local team .
VLSI Design Engineer - TES - STG - ISTL (RLM /Layout)
GOM Code : STG-0251181Relevant Experience : 8 years +
Total Experience : 12 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Active hands on experience in custom VLSI circuit layout using industry leading tools, in particular CADENCE Virtuoso XL . Familiar with custom layout, layout verification methodologies, and design for yield and manufacturability.Familiar with Cadence routing tools such as IC Craftsman is a plus.Ability to write CADENCE “SKILL” programming is a plus Basic understanding of CMOS technology and devices.CMOS Circuit Design knowledge would be advantageous.Work in a Team with Circuit Designer, Integrator and Timing Lead designing next generation microprocessors in cutting edge technology.Responsible for a number of custom layouts which meet timing, power, noise and electromigration requirements.Schematic driven placement and routing of custom macros, run Physical Design tools to generate the layout in Cadence Design Environment (Virtuoso XL).Run all necessary Physical Design (PD) rule checks like DRC, LVS, meth, etc.Optimize Interconnections (Resistivity, Capacitance) for area and delay.Optimize design for Yield and Manufacturability.“Skill” programming for enhanced layout productivity.Deliver all cadence design data according to schedule in required quality.
DRC coding/LVS coding/Parasitic extraction
GOM Code : STG -0260363Relevant Experience : 3 years +
Total Experience : 10 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Candidate for DRC coding/LVS coding/Parasitic extraction (PEX)/pcell deck development.The engineer will design pcells/DRC deck/LVS deck and/or PEX decks for both testsite and Process Development Kits. He must have experience in layout design of custom analog circuits and/or devices. Knowledge of skill & other scripting language and indsutry standard EDA tools is must. Good understanding of DRC rules is must. Knowledge of CMOS technology is highly desirable. He should have knowledge of following EDA tools - (1) Cadence's Assura DRC/LVS/Parasitic extraction tools. (2) Calibre DRC/LVS/Parasitic extraction tools. (3) Cadence Virtuoso.B.Tech. with 3 years or M.Tech. with 2 years or Ph.D. with 1 year industry experience required.
C# Developer - Websphere SWG - ISL
GOM Code : SWG -0260369Relevant Experience : 3 Years +
Total Experience : 7 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
Developer on the WebSphere MQ Product and it’s Clients. In this role will be responsible for Design, Development & Testing of new features of the product for it's upcoming Releases. Will also be responsible for reengineering code as required to match Customer requirements.Should have strong skills in C# programming and on .Net Framework. Product development experience is desired.
C# Test Developer - Websphere SWG - ISL
GOM Code : SWG-0260371Relevant Experience : 3 Years +
Total Experience : 7 years
Joining Location : Bangalore
Interview Location : Will be communicated post candidate screening and selection
Description :
This role is for developing Test Applications on WebSphere MQ Product and its Clients. They participate in Test Planning activities and develop the test design with direction from the Test Architect. They evaluate the non-functional requirements for testability and participate in the review of the technical acceptance criteria. They develop the test scenarios and test cases for verifying that the "system is built right". Usually considered a technical expert in their field, focuses on testing of Performance, Security, Load and Capacity, Networks and Infrastructure.Should have strong skills in Product Testing and C# programming. Additionally Perl Scripting skills are also required.
Targeted University Fresher Hiring : ASIC & IP
GOM Code : STG-0251181Relevant Experience : 0-18 Months
Total Experience : 0-18 Months
Joining Location : Bangalore
Interview Location : Bangalore
Description :
Processor Performance Modeling - Skills & Qualification - Candidates to be considered for this job are required to have thorough understanding of microprocessor architecture (power/intel/arm/pa-risc), cache hierarchies, cache coherency protocols, event & cycle driven modeling, strong C/C++ programming skills is essential. Having worked on architectural timing simulators, performance correlation and benchmark, workload analysis/characterization is an added bonus. Degree : ME / MTech / MS / Phd - CGPA = Minimum 7:00,Branch: CSE / ECE / Microelectronics,Colleges: IIT's / NIT's / IISc / Univ of Florida-Gainesville / Georgia Institute of Technology, Atlanta / Oklahoma State University / North Carolina State University, Raleigh /University of Washington, Seattle, USA etc,Year of Graduation: 2008 / 2009 Pass out
Targeted University Fresher Hiring : SRDC
GOM Code : STG-0251181Relevant Experience : 0-18 Months
Total Experience : 0-18 Months
Joining Location : Bangalore
Interview Location : Bangalore
Description :
The candidate should have sound background in Electrical Engineering, Solid State Physics and Devices, and basic measurement and instrumentation techniques. Wafer processing, semiconductor process development, test & measurement methodology experience desired; knowledge of Statistics is a plus.The job involves data collection and analysis of electrical parametric studies for process development methods in state of the art wafer fab for advanced technologies. Successful candidate will be required to interact with wafer fab engineers in New York routinely and provide recommendations on process enhancement and process changes. The process under development will need to be characterized with suitable electrical and physical analysis techniques, root cause analysis of failures and change recommendation leading to yield enhancement.Degree : ME / MTech / MS / Phd - CGPA = Minimum 7:00,Branch: CSE / ECE / Microelectronics,Colleges: IIT's / NIT's / IISc / Univ of Florida-Gainesville / Georgia Institute of Technology, Atlanta / Oklahoma State University / North Carolina State University, Raleigh /University of Washington, Seattle, USA etc,Year of Graduation: 2008 / 2009 Pass out
Targeted University Fresher Hiring : EDA
GOM Code : STG-0251181Relevant Experience : 0-18 Months
Total Experience : 0-18 Months
Joining Location : Bangalore
Interview Location : Bangalore
Description :
The team is working on various areas of EDA software development, and testing. Development activities include physical design automation, timing analysis, circuit level design automation, verification, graphical user interface development, System Test.Degree : ME / MTech / MS / Phd - CGPA = Minimum 7:00,Branch: CSE / ECE / Microelectronics,Colleges: IIT's / NIT's / IISc / Univ of Florida-Gainesville / Georgia Institute of Technology, Atlanta / Oklahoma State University / North Carolina State University, Raleigh /University of Washington, Seattle, USA etc,Year of Graduation: 2008 / 2009 Pass out
Targeted University Fresher Hiring : Processor Development
GOM Code : STG-0251181Relevant Experience : 0-18 Months
Total Experience : 0-18 Months
Joining Location : Bangalore
Interview Location : Bangalore
Description :
The Processor and System ASIC Front End group are currently working on leading edge processors that are the backbone of our Power and Storage servers, the IO-processing, cryptography , memory-controller asics associated with this and several embedded processors. The teams are engaged in the unit verification, logic design and pervasive design and verification on these processors. We are looking for motivated engineers who would work on hardware verification environments , debug, creating and maintaining test environment/checkers/monitors, bug coverage, test plans. Skills preferred : Good digital-hardware understanding/knowledge, VHDL, Verilog, C, C++, scripting in perl.Degree : ME / MTech / MS / Phd - CGPA = Minimum 7:00,Branch: CSE / ECE / Microelectronics,Colleges: IIT's / NIT's / IISc / Univ of Florida-Gainesville / Georgia Institute of Technology, Atlanta / Oklahoma State University / North Carolina State University, Raleigh /University of Washington, Seattle, USA etc,Year of Graduation: 2008 / 2009 Pass out
Targeted University Fresher Hiring : Systems Engineering
GOM Code : STG-0251181Relevant Experience : 0-18 Months
Total Experience : 0-18 Months
Joining Location : Bangalore
Interview Location : Bangalore
Description :
Processor Performance Modeling - Skills & Qualification - Candidates to be considered for this job are required to have thorough understanding of microprocessor architecture (power/intel/arm/pa-risc), cache hierarchies, cache coherency protocols, event & cycle driven modeling, strong C/C++ programming skills is essential. Having worked on architectural timing simulators, performance correlation and benchmark, workload analysis/characterization is an added bonus. Degree : ME / MTech / MS / Phd - CGPA = Minimum 7:00,Branch: CSE / ECE / Microelectronics,Colleges: IIT's / NIT's / IISc / Univ of Florida-Gainesville / Georgia Institute of Technology, Atlanta / Oklahoma State University / North Carolina State University, Raleigh /University of Washington, Seattle, USA etc,Year of Graduation: 2008 / 2009 Pass out
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