[EXP] Infotech hiring embedded engineering professionals

Hi Friends,

Infotech is conducting walk-in interviews on April 25^th April, 2010 (Sunday) @ Chennai.

Date : April 25^th April, 2010 (Sunday)

Time : 10:00 A.M. to 03:00 P.M.

Venue : DBS Corporate Club,
31-A Cathedral Garden Road,
Near Palmgrove Hotel,
Nugambakkam,
Chennai - 600 034
Tel : 044-40509200 / 04-23113724
Mob : 092463-72722

If you are unable to make it to the walk-in, please e-mail your resume to : Hitech.Careers@infotech-enterprises.com with Job Code

Note : Please come with your relevant documents for the interview (academics, experience letters, latest pay-slips etc)


Embedded Software
Job Code (EMBSW)
Engineers / Leads (Bengaluru)
B.E. / B.Tech or M.E / M.Tech in ECE / EEE / CSE with 3 - 9 years of experience in any of the following areas:

• RTOS and OS internals and mobile framework platforms (Linux, WinCE, Android, MAEMO)
• Firmware and Device Driver development for Mobile and Set Top Box (Connectivity / MM / Memor Devices and HID
• Experience in Pre and Post silicon validation
• Porting of protocol Stacks (GPS / AGPS, BT, WLAN), Middleware, knowledge of Telephony Frameworks
• Developing Board Support Package (BSP), boot loaders, OS porting and bring up on emulators / simulators / SDPs
• Good understanding of processor (ARM, MIPS, x86) and Overall System architecture
• System Integration & Testing (White Box) experience, Scripting knowledge
• C / C++ and Assembly Programming skills
• Android experience will be an advantage and cadidates with customer interfacing skills will be given preference.

ASIC Design
Job Code : ASIC Design
Engineers / Leads (Bengaluru)
B.E. / B.Tech or M.E / M.Tech / MS in ECE / EEE with 4+ years of experience in any of the following areas:
Physical Design : Partitioning, IO ring preparation, Floorplanning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Integrity, Low Power design

Implementation : Logic Synthesis, Low Power Synthesis, Timing Constraint, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification.

Logic Design : Microarchitecture, Logic Design, RTL Coding, Logic Synthesis, Expertise on ARM and designing subsystems around them. C / C++, Verlog / VHDL, System Verilog


Hardware Design
Job Code : (EMBHRDW)
Engineers / Leads (Bengaluru)
B.E. / B.Tech or M.E / M.Tech in ECE / EEE with 4+ years of experience in any of the following areas:

• Responsibilities include design of analog and digital circuits with hands-on experience on simulation of the circuits using Pspice / Multisim
• Performing circuit analysis like worst case, stress and root cause analysis
• Design of circuits with 8/16/32 bit microcontrollers
• Designing power electronics circuits
• Carry out schematic entry, PCB design and layout using Cadence / Orcad tools
• Prepare test plan, testing of the hardware and generate test results
• Experience on Avionics domain and standard like D0254, D0160E is and added advantage
• knowledge on the tools like DOORS and VSS is preferred
• Knowledge on design of FPGA / DS based circuit is optional.

Candidates need not walk-in for the position mentioned below. Send your resume to Hitech.Careers@infotech-enterprises.com

ASIC Design
Job Code (ASIC Design)
Verification : Block level and Sysem level (SoC) verification ARM / MIPS Power PCbased SoC Verification, Test Bench development, Test Cases development, BFM models, coverage driven verification, Gate level simulations, Veilog / VHDL, system Verlog / Specman / Vera, C / C++, VMM / RVM / OVM verification.