Date | 9-Apr-2011 (Saturday) |
Venue | TCS Salarpuria G. R. Tech Park, Dhara Block, K R Puram, Bangalore 560 066 |
Registration Time | 9:00am -12:00Noon |
Skills | Experience Band | Requirement (JD) |
FPGA validation | 2 to 7yrs | Verification (mandatory) a) Ability to architect and implemented automated verification environment and test cases / procedures (HDL-based: VHDL / Verilog). b) Experienced in requirements-based, targeted verification with traceability c) Experienced in achieving Code Coverage closure d) Familiar with DO-254 Design experience (preferred) a) Ability to translate requirements into design partitions, design units, FSMs b) Experience with Logic Synthesis, Static Timing Analysis and FPGA P&R |
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